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KS88C2064
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
KS88-SERIES MICROCONTROLLERS
Samsung's KS88 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include: -- Efficient register-oriented architecture -- Selectable CPU clock sources -- Idle and Stop power-down mode release by interrupt -- Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels.
KS88C2064 MICROCONTROLLER
The KS88C2064 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung's newest CPU architecture. The KS88C2064 is the microcontroller which has 64-Kbyte mask-programmable ROM and 192-Kbyte mask ROM for font data. Using a proven modular design approach, Samsung engineers developed the KS88C2064 by integrating the following peripheral modules with the powerful SAM87 core: -- Four programmable I/O ports, excluding one BUZ pin, for a total of 32 pins. -- Eight bit-programmable pins for external interrupts. -- One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset). -- One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. -- Watch timer for real time. The KS88C2064 is a versatile microcontroller for data bank or dictionary. It is currently available in a 128-pin QFP package.
1-1
PRODUCT OVERVIEW
KS88C2064
FEATURES
CPU * SAM87 CPU core LCD Controller/Driver * * * * 65 segments and 18 common terminals Internal resistor circuit for LCD bias Voltage doubler All dot can be switched on/off
Memory * * * * 64-Kbyte internal program memory (ROM) 192-Kbyte internal memory (ROM) for font data 272-byte internal register file (Excluding LCD RAM) 6144-byte data RAM
Timers and Timer/Counters * One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer (software reset) function One 8-bit timer/counter (Timer 0) with three operating modes; Interval, Capture and PWM One 16-bit timer/counter (Timer 1) with two 8bit timer/counter modes; Interval
Instruction Set * * 78 instructions IDLE and STOP instructions added for power-down modes
* *
Instruction Execution Time * * 1.5 s at 4 MHz fx (minimum) 183 s at 32,768 Hz fxt
Power-Down Modes * * Idle mode (CPU clock stops) Stop mode (main oscillation and CPU clock stops)
Interrupts * * * Five interrupt levels and 15 interrupt sources 15 vectors (15 sources have a dedicated vector address) Fast interrupt processing feature (for one selected interrupt level) Operating Temperature Range * - 40 C to + 85 C
Operating Voltage Range * * 2.2 V to 4.5 V at 1 MHz fx 2.7 V to 4.5 V at 4 MHz fx
I/O Ports * * * Four 8-bit I/O ports (P0-P3) for a total of 32-bit programmable pins Eight input pins for external interrupts One output only pin for BUZ
Package Type * 128-pin QFP
Watch Timer * * * Interval time: 3.91 ms, 1s at 32,768 Hz Four frequency outputs to BUZ pin and BUZ pin Clock source generation for LCD
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KS88C2064
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0-P0.7 (A8-A15)
P1.0-P1.7 (AD0-AD7)
RESET
Port 0
Port 1
TEST P2.0-P2.3 (AS, DW, DR, DM ) P2.4-P2.7 (T0, T0CK, CLO, BUZ) P3.0/TB/INT0 P3.1/TA/INT1 P3.2/T1CK/INT2 P3.3/INT3 P3.4/INT4 P3.5/INT5 P3.6/INT6 P3.7/INT7 COM0-COM8 COM9-COM17 SEG0-SEG64 VLC0 BIAS CA CB TA TB T1CK
Basic Timer
Internal Bus Port 2
XIN XOUT
I/O Port and Interrupt Control Main OSC Port 3
XTIN XTOUT
Sub OSC
SAM8 CPU LCD Driver/ Controller 64-Kbyte ROM 314-Byte Register File Voltage Doubler
BUZ
BUZ
Watch Timer
T0
Timer 0
T0CK
Timer 1
192-Kbyte Font ROM
6144-Byte Data RAM
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
KS88C2064
PIN ASSIGNMENTS
SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 VDD VSS XOUT XIN TEST XTIN XTOUT
RESET
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35
KS88C2064
(128-QFP-1420)
P0.7/A15 P0.6/A14 P0.5/A13 P0.4/A12 P0.3/A11 P0.2/A10 P0.1/A9 P0.0/A8 P1.7/AD7 P1.6/AD6 P1.5/AD5
SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8
P1.4/AD4 P1.3/AD3 P1.2/AD2 P1.1/AD1 P1.0/AD0 P3.0/TB/INT0 P3.1/TA/INT1 P3.2/T1CK/INT2 P3.3/INT3 P3.4/INT4 P3.5/INT5 P3.6/INT6 P3.7/INT7 P2.0/AS P2.1/DW P2.2/DR P2.3/DM P2.4/T0 P2.5/T0CK P2.6/CLO P2.7/BUZ
Figure 1-2. Pin Assignment (128-Pin QFP Package)
1-4
CA CB VLC0 BIAS
BUZ
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
KS88C2064
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. Pin Descriptions Pin Names P0.0-P0.7 Pin Type I/O Pin Description I/O port with nibble-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up; also configurable as external interface address lines A8-A15. Same general characteristics as port 0; also configurable as external interface address/data lines AD0-AD7. I/O port with bit-programmable pins; schmitt trigger input or push-pull output and software assignable pull-ups. Lower nibble pins 0-3 are configurable for external interface signals. P2.4/capture input, interval/PWM output (T0) P2.5/timer 0 clock input (T0CK) P2.6/system clock output (CLO) P2.7/buzzer signal output (BUZ) I/O port with bit-programmable pins; schmitt trigger input or push-pull output and software assignable pull-up; P3.0-P3.7 are alternately used for external interrupt input (noise filters, interrupt enable and pending control); P3.0/timer B clock output (TB)/INT0 P3.1/timer 1/A clock output (TA)/INT1 P3.2/timer 1/A clock input (T1CK)/INT2 Timer A external clock input pins. Timer B and 1/A clock output pins. Output pins for external interface control signals. AS: address strobe DW: data memory write DR: data memory read DM: data memory select Capture input or interval/PWM output. Timer 0 clock input. Circuit Type 3 Pin No. 35-28 Shared Functions A8-A15
P1.0-P1.7
I/O
3
43-36
AD0-AD7
P2.0-P2.3
I/O
5
52-55
AS, DW, DR, DM
P2.4-P2.7
I/O
6
56-59
T0, T0CK, CLO, BUZ
P3.0-P3.7
I/O
4
44-51
TB/INT0, TA/INT1, T1CK/INT2, INT3-INT7
T1CK TB TA
AS, DW, DR, DM
I/O I/O I/O
4 4 5
46 44 45 52-55
P3.2/INT2 P3.0/INT0 P3.1/INT1 P2.0-P2.3
T0 T0CK
I/O I/O
6 6
56 57
P2.4 P2.5
1-5
PRODUCT OVERVIEW
KS88C2064
Table 1-1. Pin Descriptions (Continued) Pin Names CLO BUZ
BUZ
Pin Type I/O I/O O I/O Clock output
Pin Description
Circuit Type 6 6 - 4
Pin No. 58 59 60 44-51
Shared Functions P2.6 P2.7 - P3.0/TB, P3.1/TA, P3.2/T1CK, P3.3-P3.7 P1.0-P1.7 P0.0-P0.7 - - - - - - - - - - -
Output pin for buzzer signal. Inverted buzzer signal output. External interrupt input pins.
INT0-INT7
AD0-AD7 A8-A15 COM0-COM8 COM9- COM17 SEG0- SEG64 CA, CB VLC0 BIAS
RESET
I/O I/O O O O - - O I - I - -
Address low and data ports. Address high output ports. LCD common signal output. LCD common signal output. LCD seg signal output. Capacitor terminal for voltage doubling. LCD power supply. Bias voltage level for LCD driving. System reset pin Crystal oscillator pins for sub clock. Test signal input (must be connected to VDD). Main oscillator pins Power input pins
3 3 7 7 8 - - - 2 - - - -
43-36 35-28 73-65 11-19 10-1 128-74 61, 62 63 64 27 25, 26 24 23, 22 20, 21
XTIN, XTOUT TEST XIN, XOUT VDD, VSS
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KS88C2064
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD Pull-up Resistor
P-Channel In In N-Channel
Schmitt Trigger
Figure 1-3. Pin Circuit Type 1
Figure 1-4. Pin Circuit Type 2 (RESET)
VDD Pull-up Resistor Pull-up Enable VDD
Data I/O Open-drain Output Disable VSS Input
Figure 1-5. Pin Circuit Type 3 (Ports 0, 1)
1-7
PRODUCT OVERVIEW
KS88C2064
PIN CIRCUIT DIAGRAMS (Continued)
VDD Pull-up Resistor Pull-up Enable VDD Data I/O Output Disable External Interrupt Input Noise Filter VSS
Input
Figure 1-6. Pin Circuit Type 4 (Port 3)
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KS88C2064
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS (Continued)
VDD Pull-up Resistor Pull-up Enable Port 2 (Low Byte) Data External Interface (AS, DW, DR, DM ) Select VDD M U X Data
I/O Output Disable VSS Input
Figure 1-7. Pin Circuit Type 5 (Ports 2.0-2.3)
VDD Pull-up Resistor Pull-up Enable VDD Data I/O Output Disable VSS Input
Figure 1-8. Pin Circuit Type 6 (Ports 2.4-2.7)
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PRODUCT OVERVIEW
KS88C2064
PIN CIRCUIT DIAGRAMS (Continued)
VLC0
VLC1
COM
Out
VLC4
VSS
Figure 1-9. Pin Circuit Type 7 (COM0-COM17)
VLC0
VLC2
SEG
Out
VLC3
VSS
Figure 1-10. Pin Circuit Type 8 (SEG0-SEG64)
1-10
KS88C2064
ELECTRICAL DATA
15
OVERVIEW
-- -- -- -- -- -- -- -- -- -- --
ELECTRICAL DATA
In this chapter, KS88C2064 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: Absolute maximum ratings D.C. electrical characteristics Data retention supply voltage in Stop mode Stop mode release timing when initiated by an external interrupt Stop mode release timing when initiated by a Reset I/O capacitance A.C. electrical characteristics Input timing for external interrupts (port 0, P2.3-P2.0) Input timing for RESET Oscillation characteristics Oscillation stabilization time
15-1
ELECTRICAL DATA
KS88C2064
Table 15-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current High Output current Low Operating temperature Storage temperature Symbol VDD VIN VO IOH Ports 0, 1, 2, and 3 All output pins One I/O pin active All I/O pins active IOL One I/O pin active Total pin current for ports 0-3 TA TSTG - - Conditions - Rating - 0.3 to + 5.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 18 - 60 + 30 + 100 - 40 to + 85 - 65 to + 150
C C
Unit V V V mA
mA
15-2
KS88C2064
ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.2 V to 4.5 V) Parameter Input High voltage Symbol VIH1 VIH2 VIH3 Input Low voltage VIL1 VIL2 VIL3 Output High voltage Output Low voltage Input High leakage current VOH VOL ILIH1 Conditions All input pins except VIH2 and VIH3
RESET
Min 0.8 VDD 0.8 VDD VDD - 0.5 0
Typ -
Max VDD VDD VDD 0.2 VDD 0.2 VDD 0.5
Unit V
XIN, XTIN All input pins except VIL2 and VIL3
RESET
-
XOUT, XTOUT VDD = 3.0 V; IOH = - 1 mA All output pins VDD = 3.0 V; IOL= 2 mA All output pins VIN = VDD; all input pins except XIN, XOUT, XTIN, and XTOUT VIN = VDD; XIN, XOUT, XTIN, and XTOUT VIN = 0 V; all input pins except XIN, XOUT, XTIN, and XTOUT VIN = 0 V; XIN, XOUT, XTIN, and XTOUT VOUT = VDD All output pins VOUT = 0 V All output pins - - - - - - VDD - 1.0 - - - - -
- 1.0 1 A
ILIH2 Input Low leakage current ILIL1
20 -1
ILIL2 Output High leakage current Output Low leakage current ILOH ILOL
- 20 1 -1
15-3
ELECTRICAL DATA
KS88C2064
Table 15-2. D.C. Electrical Characteristics (Continued) (TA = - 40C to + 85C, VDD = 2.2 V to 4.5 V) Parameter Middle output voltage Symbol VOM1 VOM2 VOM3 VOM4 |VLCD-VCOMi| voltage drop (i = 0-17) |VLCD-VSEGx| voltage drop (x = 0-64) LCD driving voltage Pull-up resistors VDC x VLCD N = 1, 2, 3, and 4 Conditions VMN = VLCD - (N/5) COM0-17 SEG0-64 SEG0-64 COM0-17 VLCD = 3.0 V to 6.0 V - 15 A per common pin VLCD = 3.0 V to 6.0 V - 15 A per common pin - VIN = 0 V; TA = 25 C; VDD = 3.0 Ports 0, 1, 2, and 3 VIN = 0 V; TA = 25 C; VDD = 3.0 RESET only VLCD = 3.0 V to 6.0 V TA = 25 C VDD = 3.0 V 10% 2 MHz crystal Idle mode; VDD = 3.0 V 10% 2 MHz crystal VDD = 3.0 V 10% 32 kHz crystal Idle mode; VDD = 3.0 V 10% 32 kHz crystal Stop mode; VDD = 3.0 V 10% XTIN = 0 V Min VM1 - 0.2 VM2 - 0.2 VM3 - 0.2 VM4 - 0.2 - Typ VM1 VM2 VM3 VM4 - Max VM1 + 0.2 VM2 + 0.2 VM3 + 0.2 VM4 + 0.2 120 mV Unit V
VDS
-
-
120
mV
VLCD RL1 RL2
3.0 30 300 40 -
- 80 500 60 1.5 0.5
6.0 200 800 80 3.5 1.5
V k
LCD voltage dividing resistor Supply current
(note)
RLCD IDD1 IDD2
k mA
IDD3 IDD4
30 6
70 12
A
IDD5
0.5
1
NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, voltage doubler, or external output current loads. 2. IDD1 and IDD2 include power consumption for subsystem clock oscillation. 3. IDD3 and IDD4 are current when main system clock oscillation stops and the subsystem clock is used.
15-4
KS88C2064
ELECTRICAL DATA
Table 15-3. Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 2.2 V - Released by RESET Released by interrupt Min 2.2 - 0 - - Typ - - - 216/fx (1)
(2)
Max 4.5 5 - - -
Unit V A s ms
NOTES: 1. fx is the main oscillator frequency.
2. The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON.
Idle Mode (Basic Timer Active) Stop Mode Data Retention Mode Normal Operating Mode
~ ~ ~ ~
VDD
VDDDR Execution of STOP Instrction 0.8 VDD tWAIT Interrupt Request
Figure 15-1. Stop Mode Release Timing When Initiated by an External Interrupt
15-5
ELECTRICAL DATA
KS88C2064
RESET
Occurs
Oscillation Stabilization Time Normal Operating Mode
~ ~ ~ ~
Stop Mode Data Retention Mode
VDD
VDDDR Execution of STOP Instrction
RESET
tSRL
0.8 VDD 0.2 VDD tWAIT
Figure 15-2. Stop Mode Release Timing When Initiated by a RESET
15-6
KS88C2064
ELECTRICAL DATA
Table 15-4. Input/Output Capacitance (TA = - 40 C to + 85 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min - Typ - Max 10 Unit pF
Table 15-5. A.C. Electrical Characteristics (TA = - 40 C to + 85 C) Parameter Interrupt input, High, Low width
RESET input Low
Symbol tINTH, tINTL tRSL
Conditions P3.0-P3.7 VDD = 3 V Input VDD = 3 V
Min 500 2000
Typ 700 -
Max - -
Unit ns
width
Table 15-6. Voltage Doubler Output (TA = - 40 C to + 85 C) Parameter Voltage Doubler Output Symbol VBIAS Conditions VDD = 3 V 10 % only Min 2 VDD - 0.5 Typ 2 VDD Max 2 VDD + 0.5 Unit V
tINTL
tINTH
0.8 VDD 0.2 VDD
NOTE:
The unit t CPU means one CPU clock period.
Figure 15-3. Input Timing for External Interrupts (P3.0-P3.7)
15-7
ELECTRICAL DATA
KS88C2064
tRSL
RESET
0.3 VDD
Figure 15-4. Input Timing for RESET Table 15-7. Main Oscillation Characteristics (TA = - 40 C + 85 C, VDD = 2.2 V to 4.5 V) Oscillator Crystal Clock Circuit
XIN XOUT
Conditions CPU clock oscillation frequency
Min 0.4
Typ -
Max 4
Unit MHz
C1
C2
Ceramic
XIN XOUT
CPU clock oscillation frequency
0.4
-
4
MHz
C1
C2
External clock
XIN XOUT
XIN input frequency
0.4
-
4
MHz
RC
XIN
XOUT
Frequency, VDD = 3 V
0.4
-
2
MHz
15-8
KS88C2064
ELECTRICAL DATA
Table 15-8. Sub Oscillation Characteristics (TA = - 40 C + 85 C, VDD = 2.2 V to 4.5 V) Oscillator Crystal Clock Circuit
XIN XOUT
Conditions CPU clock oscillation frequency
Min 32
Typ 32.768
Max 35
Unit kHz
C1
C2
External clock
XIN XOUT
XTIN input frequency
32
-
500
kHz
Table 15-9. Main Oscillation Stabilization Time (TA = - 40 C + 85 C, VDD = 3.0 V 10 %) Oscillator Crystal Ceramic External clock fx > 400 kHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input High and Low width (tXH, tXL) Test Condition Min - - 25 Typ - - - Max 80 50 700 Unit ms ms ns
1/fx tXL tXH
XIN
VDD - 0.5 V 0.5 V
Figure 15-5. Clock Timing Measurement at XIN
15-9
ELECTRICAL DATA
KS88C2064
Table 15-10. Sub Oscillation Stabilization Time (TA = - 40 C + 85 C, VDD = 3.0 V 10 %) Oscillator Crystal External clock Test Condition - XIN input High and Low width (tXH, tXL) Min - 1 Typ 1.0 - Max 2 18 Unit s s
1/fxt tXTL tXTH
XTIN
VDD - 0.5 V 0.5 V
Figure 15-6. Clock Timing Measurement at XTIN
15-10
KS88C2064
ELECTRICAL DATA
Instruction Clock 666 kHz 333 kHz 167 kHz
fx (Main oscillation frequency) 4 MHz 2 MHz 1 MHz
400 kHz
8.32 kHz 2 2.2 2.4 2.7 3 4 4.5 5
Supply Voltage (V) Instruction Clock = 1/6n x oscillator frequency ( n = 1, 2, 8, 16)
Figure 15-7. Operating Voltage Range
15-11
KS88C2064
MECHANICAL DATA
16
OVERVIEW
MECHANICAL DATA
The KS88C2064 microcontroller is currently available in a 128-pin TQFP package.
22.00 0.30 20.00 0.20 0-8
+ 0.10
0.15 - 0.05
0.30
0.20
16.00
14.00
128-QFP-1420
0.10 MAX
(0.75)
#1 0.50
0.20
+ 0.10 - 0.05
0.05 MIN 0.10 MAX (0.75) 2.10 0.10 2.40 MAX
0.10 MAX 0.50
0.20
NOTE: Dimensions are in millimeters.
Figure 16-1. 128-Pin TQFP Package Mechanical Data
0.50
#128
0.20
16-1

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